1. Field of the Invention
The present invention relates to a digital proportional integral loop filter for fast settling time, and more particularly, to a digital proportional integral loop filter capable of changing a loop filter gain through one-time switching to thereby change a loop filter coefficient even with a great change in loop filter gain by generating offsets using a phase error average value and a phase error accumulation average value, and capable of locking to a single desired frequency at a time to thereby reduce settling time.
2. Description of the Related Art
A conventional analog phase locked loop (PLL) including a phase/frequency detector, a charge pump, and an RC loop filter has been replaced with an all-digital PLL (ADPLL) including a time-to-digital converter and a simple digital loop filter. This is because signal processing can be performed with a digital circuit capable of avoiding dependency on a fine voltage resolution of an analog circuit. A new technology for an ADPLL digital loop filter has been proposed which has rapid frequency acquisition time while maintaining superior phase noise characteristics and spurious performance by applying a digital signal processing scheme to a loop filter.
FIG. 1 illustrates a related art proportional loop filter 100 using a gear-shift scheme. The proportional loop filter 100 using the gear-shift scheme includes bit shifters 120 and 121, adders 140 and 143, and a multiplexer 150. The bit shifters 120 and 121 acts as a multiplier and a divider. The multiplexer 150 outputs a value 130 of α1·φE[k] when a tracking mode control signal is 0, and outputs the sum of a value 131 of α2·φE[k] and a value 142 of ΔNTW when the tracking mode control signal is 1.
An output of a phase detector 101 is inputted to the proportional loop filter 100. A PLL loop gain value must be large in order to quickly reduce a settling time of an ADPLL, and must be small in order to obtain superior phase noise characteristics. To meet both of the opposite characteristics, a gear-shift scheme is used.
The case wherein the tracking mode control signal is 0 means that the acquisition of a fast settling time is desirable. In this case, the value α1 is selected so that a bandwidth of the ADPLL is widened, and the value 130 of α1·φE[k] is outputted as the output of the loop filter. The case wherein the tracking mode control signal is 1 means that superior phase noise characteristic is desirable. In this case, the value α2 (<α1) is selected so that the loop bandwidth is narrowed to reduce noise, and the value 131 of α2·φE[k] is outputted.
However, if the output of the loop filter abruptly changes from α1·φE[k] as the value 130 to α2·φE[k] as the value 131, the frequency locking of the ADPLL may be unlocked.α1·φE[k](130)=α2·φE[k](131)+ΔNTW  (1)
If the offset value 142 of ΔNTW is added as expressed in Equation (1), the phase error value is maintained at the same value as before the change, even though the loop filter gain is changed. Thus, the frequency locking of the ADPLL is not unlocked, and noise is reduced because the loop bandwidth is narrowed.ΔNTW(142)=(α1−α2)·φE[k]  (2)
The offset value may be calculated from Equation (2) under the conditions of Equation (1).
Since the hardware sizes of the multiplier and the divider are large, the bit shifters 120 and 121 may be used if a corresponding to the square of 2 is used. Thus, the size and complexity of the required hardware are reduced.
The output of the multiplexer 150 is the output 151 of the loop filter 100, and is inputted to a digitally controlled oscillator (DCO) 160. In the loop filter using the gear-shift scheme, noise may be further added at the moment when the gear shift is switched. When the difference between α1 and α2 is great, the gear shift may not find the frequency corresponding to α2 at a time, and a settling time for a desired frequency value is required. Therefore, in order to reduce the settling time and improve the phase noise characteristic, the amount of shift switching must be increased by changing the loop filter gain value in sequence, for example, 2−2→2−4→2−6. Furthermore, there may be a problem in the stability of the ADPLL because the gear shift of the loop filter gain is applied only to the proportional loop filter structure.